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We're halfway through!

Coagulated and arranged the components on PCB.

I'll ask Rohit to help me verify the VHDCI footprint by taking a printout of this and checking it against the VHDCI connector he has for right fit and correct alignment.

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• As usual, fixed issues and created components and footprints. Done with CvPcb on all daughterboards. GPIO-25 and LED are remaining.
• I don't know how useful the LED daughterboard is, knowing that the serial port lines are not bidirectional. Have to ask my mentor.
• Created daughterboard slot schematic component and daughterboard slot modules that map to each other can can be changed conveniently. The footprint is 90x40 mm

• Started arranging components on motherboard PCB, here's a peek:

• Ignore the placement of reddish components, I have just started and have to arrange things nicely :)

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• Created footprints, completed footprint associations and started a PCB with components laid out for RS232C, RS422, DMX512, GPIO8, IR and MIDI daughterboards.
• Rough estimate of maximum daughterboard PCB length:

IR daughterboard: 70 mm
DMX512 daughterboard: 75 mm
RS422 daughterboard: 90 mm
GPIO8 daughterboard: 65 mm
RS232 daughterboard: 60 mm
MIDI daughterboard: 70 mm

• 90 mm seems minimum daughterboard length to have.
• Will start arranging components on motherboard PCB, with minimum keepout length of 90 mm for daughterboard slots and will see if there is space for setting daughterboard length greater than 90 mm.

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• After starting with motherboard PCB design, the very next thing that needed to be done was designing the daughterboard slot footprint, which needed me to decide a depth of the daughterboard.
• I did not have a basis for deciding the depth, so I thought it is necessary to complete the daughterboard schematics and I completed the remaining daughterboard schematics yesterday and fixed a number of issues with existing schematics - 36 commits!
• MIDI daughterboard schematics are based on this: http://www.personal.kent.edu/~sbirch/Music_Production/MP-II/MIDI/midi_physical_layer.htm
• I have completed footprint assignments (CvPcb) and laid out components for RS232C daughterboard (PcbNew)

• I plan to start PCBs for other daughterboards to spread out components and see how much space they would require and decide a depth.
• After that I'll get back to motherboard schematics.
• Not sure if the LED daughterboard has a use, since the serial lines are no bidirectional we can't connect LEDs directly. If it's done through a microcontroller we can probably use the GPIO daughterboard instead.

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• Changed daughterboard pinouts in schematics support PMOD I2C interface.
• Looked at the possibility of using bidirectional isolators in data isolation stage, but it was ruled out as they were found to be expensive.
• Re-justified use of data isolation stage in serial expansion motherboard.
• Created new kicad modules (footprints)
• Completed footprint association of components on motherboard schematics using CvPcb
• Verified footprints for components and checked 0603 footprint to be imperial type instead of metric type. Checked datasheets of all components to make sure correct footprint is assigned to them.
• Made sure only low current (2mA) LEDs are used.
• Fixed hole dia and added shield pins in VHDCI module
• Just started with PcbNew, will be creating new module for the daughterboard slot and start laying them out nicely.

Week 6: Time for PCBs!

Motherboard schematics are ready and we’re all set to do the PCBs for motherboard! Last week was spent on organizing the repository, schematics and making various decisions that affected schematics. There is slightly more work to be done on daughterboards schematics and it needs more reviews and fixing.

We began this week by figuring out the best possible autodetection scheme. We discussed about possible use cases for autodetection and how different autodetection schemes would fit into it. First scheme was measuring RC time constant using an I/O pin on the daughterboard. The problem with this scheme was that the RC time-constant measurement using an I/O pin is prone to errors since it depends on logic level thresholds of the I/O pin, which are not clearly documented and their errors are unknown. Slight change in the threshold values can affect our measurement greatly. These thresholds can depend on temperature, VCC, noise and production batch. A reliable way would be measuring the time constant using a voltage comparator and a precision voltage source. But this is the multimeter method and is a bit expensive.

I and Rohit (who’s doing VGA expansion board) settled for I2C EEPROM based detection where each daughterboard will have an inexpensive, pin addressable EEPROM storing ID and configuration data for that daughterboard. The EEPROM slave address gets set on the motherboard, the addresses depend on the slot the daughterboard is connected to.

We were also suggested to take a look on SPI daisy-chaining of EEPROMs, because that would have been the most flexible auto-detection method. I2C based method is addressed based, all EEPROMs with slave address 0 will have expansion board data and EEPROMs with higher address would have module data. If we want to connect more than one expansion board by splitting VHDCI connector, there would be an address conflict in I2C based detection. SPI daisy-chaining would solve that. But it turns out that SPI daisy chaining is not possible for the reasons documented here by Rohit.

I had completed by first run of schematics which got reviewed by Tim. There was a heap of issues with my repository as well as schematics that were fixed one by one.

This week I started the daughterboards and created templates for them. I completed first run of RS232, IR, RS422, GPIO daughterboards. And there are issues with them to solve. It’ll probably take up to a day.

I updated the requirements document to reflect our new decisions. This document never seems to finish because there’s always something new to add or update. As of now there are things to do in that document - like explaining the system diagram I made. The information related to serial communication has become quite fragmented might needs to be more organised. I have to complete the power calculation spreadsheet which will bring out some new limitations and challenges.

Goals for this week:

It seems we need to wind up the hardware part by this week. We need to:

• Finish daughterboards, get it reviewed.
• Update requirements document.
• Start PCB design, get quote from PCB manufacturers.
• Once again, check and finalize daughterboard depth, motherboard depth and width.
• (Hopefully) complete the motherboard PCB by this week.

Here’s a peek at the latest schematics as of now, which you may want to compare it with the older ones in last week’s progress report :)

Daily snippet

• RS422/RS485 daughterboard schematics done.
• Created a _common folder in repository to store common hierarchical sheets to be shared between daughterboards.
• Reduced 6 ports to 5 ports in serial expansion board.
• PIC18F connections almost sorted out with port J left vacant.
• Implemented the bus design in motherboard schematic.